Name
Abstract | ||
|---|---|---|
The continuous growth of the internet and of big data infrastructure drives the ever-increasing demand for data communication bandwidth between chips. In this context, wireline transceiver data rate, energy efficiency, and area are extremely critical. This session introduces two transceivers operating at 56Gb/s PAM-4 and 60Gb/s NRZ. It continues with a presentation of a 40–56Gb/s PAM-4 receiver with 10-tap direct decision feedback equalization in 16nm FinFET. Two papers presenting high-data-rate, low-power PAM-4 transmitter designs are presented next, including a 64Gb/s design with a 4-tap FFE in 28nm FDSOI CMOS, and a 56Gb/s design with fractionally spaced FFE in 14nm CMOS. Finally, the session concludes with two papers describing receivers at or beyond 28Gb/s, including a reference-less baud-rate CDR with DFE and CTLE in 28nm CMOS and a digital CDR with adaptive loop gain for optimum jitter tolerance. |
Year | DOI | Venue |
|---|---|---|
2017 | 10.1109/ISSCC.2017.7870284 | 2017 IEEE International Solid-State Circuits Conference (ISSCC) |
Field | DocType | ISBN |
Transmitter,Wireline,Transceiver,Loop gain,Equalization (audio),Efficient energy use,Computer science,Electronic engineering,CMOS,Jitter,Electrical engineering | Conference | 978-1-5090-3759-9 |
Citations | PageRank | References |
0 | 0.34 | 0 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Simone Erba | 1 | 51 | 8.90 |
| Takayuki Shibasaki | 2 | 66 | 12.00 |
| Frank O'Mahony | 3 | 102 | 20.28 |