Name
Title | ||
|---|---|---|
28.5 A 10b 1.5GS/s pipelined-SAR ADC with background second-stage common-mode regulation and offset calibration in 14nm CMOS FinFET. |
Abstract | ||
|---|---|---|
High-speed SAR ADCs became popular with modern CMOS technologies because of their mostly digital logic, making them highly suitable for compact and power-efficient multi-GS/s time-interleaved ADCs. As many applications cannot tolerate input swings ≥1V ppd , comparator noise limits the SNDR of SAR ADCs, making gain stages necessary for higher SNDR - either as comparator pre-amplifiers or between pipelined stages. Pre-amplifiers significantly reduce the conversion speed of the ADC, but they provide maximum SNDR because linearity of the amplifier is irrelevant. An interstage amplifier for pipelining best suits mid-resolution SAR ADCs, where the required linearity is limited. Moreover, pipelining results in higher conversion speeds and power efficiency because the gain stage is used only once per conversion [1]. This work presents a pipelined-SAR ADC architecture that exceeds the conversion speed of previous pipelined and single-stage SAR ADCs. The ADC achieves 50dB SNDR and 950MS/s at 2.26mW, and 1.5GS/s at 6.92mW on an area of 0.0016mm 2 . |
Year | Venue | Field |
|---|---|---|
2017 | ISSCC | Flight dynamics (spacecraft),Electrical efficiency,Comparator,Computer science,Linearity,Electronic engineering,Gain stage,CMOS,Successive approximation ADC,Electrical engineering,Amplifier |
DocType | Citations | PageRank |
Conference | 1 | 0.48 |
References | Authors | |
2 | 11 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Lukas Kull | 1 | 141 | 18.63 |
| Danny Luu | 2 | 16 | 7.55 |
| Christian Menolfi | 3 | 245 | 41.54 |
| Matthias Braendli | 4 | 158 | 24.28 |
| Pier Andrea Francese | 5 | 138 | 25.33 |
| Thomas Morf | 6 | 244 | 42.54 |
| Marcel A. Kossel | 7 | 179 | 33.86 |
| Hazar Yueksel | 8 | 7 | 4.15 |
| Alessandro Cevrero | 9 | 107 | 16.21 |
| Ilter Özkaya | 10 | 16 | 5.72 |
| Thomas Toifl | 11 | 275 | 48.02 |