Paper Info
Title
Architecting SOT-RAM Based GPU Register File
Abstract
With increase in GPU register file (RF) size, its power consumption has also increased. Since RF exists at the highest level in cache hierarchy, designing it with memories with high write latency/energy (e.g., spin transfer torque RAM) can lead to large energy loss. In this paper, we present an spin orbit torque RAM (SOT-RAM) based RF design which provides higher energy efficiency than SRAM and STT-RAM RFs while maintaining performance same as that of SRAM RF. To further improve energy efficiency of SOT-RAM based RF, we propose avoiding redundant bit-writes to RF. Compared to SRAM RF, SOT-RAM RF saves 18.6% energy and by using our technique for avoiding redundant writes, the energy saving can be increased to 44.3%, without harming performance.
Year
DOI
Venue
2017
10.1109/ISVLSI.2017.17
2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)
Keywords
Field
DocType
SOT-RAM,GPU register file,power consumption,cache hierarchy,spin transfer torque RAM,energy loss,spin orbit torque RAM,RF design,energy efficiency,SRAM,STT-RAM,SRAM RF,redundant bit-writes,energy saving
Tag RAM,Computer science,Efficient energy use,Register file,Static random-access memory,Radio frequency,Non-volatile memory,Computer hardware,Energy consumption,Microarchitecture,Embedded system
Conference
ISBN
Citations 
PageRank 
978-1-5090-6763-3
0
0.34
References 
Authors
17
7
Name
Order
Citations
PageRank
Sparsh Mittal1302.62
Rajendra Bishnoi213219.64
Fabian Oboril328826.71
Haonan Wang48512.41
Mehdi B. Tahoori51537163.44
Adwait Jog656823.32
Vetter, Jeffrey72383186.44