Name
Abstract | ||
|---|---|---|
Since integrating memory blocks on-chip became affordable, embedded logic analysis has been used extensively for post-silicon validation and debugging. Deciding at design time which signals to be traceable at the post-silicon phase, has been posed as an algorithmic problem a decade ago. The primary focus of the subsequent approaches on this topic was to restore as much data as possible within a so... |
Year | DOI | Venue |
|---|---|---|
2018 | 10.1109/TCAD.2017.2729458 | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems |
Keywords | DocType | Volume |
Debugging,Computer bugs,Clocks,Logic gates,System-on-chip,Design automation | Journal | 37 |
Issue | ISSN | Citations |
5 | 0278-0070 | 0 |
PageRank | References | Authors |
0.34 | 8 | 2 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Amin Vali | 1 | 1 | 0.71 |
| Nicola Nicolici | 2 | 807 | 59.91 |