Name
Abstract | ||
|---|---|---|
In this paper, we propose a method to diagnose a bridging fault between a clock line and a gate signal line. Assuming that scan based flush tests are applied, we perform fault simulation to deduce candidate faults. By analyzing fault behavior, it is revealed that faulty clock waveforms depend on the timing of the signal transition on a gate signal line which is bridged. In the fault simulation, a backward sensitized path tracing approach is introduced to calculate the timing of signal transitions. Experimental results show that the proposed method deduces candidate faults more accurately than our previous method. |
Year | DOI | Venue |
|---|---|---|
2017 | 10.1587/transinf.2016EDL8210 | IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS |
Keywords | Field | DocType |
fault diagnosis, bridging faults, clock lines | Computer vision,Computer science,Bridging fault,Real-time computing,Artificial intelligence,Computer hardware,Signal lines | Journal |
Volume | Issue | ISSN |
E100D | 9 | 1745-1361 |
Citations | PageRank | References |
0 | 0.34 | 5 |
Authors | ||
5 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Yoshinobu Higami | 1 | 140 | 27.24 |
| Senling Wang | 2 | 18 | 5.91 |
| H. Takahashi | 3 | 18 | 3.94 |
| Shin-ya Kobayashi | 4 | 3 | 3.77 |
| Kewal K. Saluja | 5 | 1483 | 141.49 |