Title
A 28-nm FD-SOI 8T Dual-Port SRAM for Low-Energy Image Processor With Selective Sourceline Drive Scheme
Abstract
This paper presents a low-energy 64-Kb eight-transistor (8T) one-read/one-write dual-port image memory with a 28-nm fully depleted SOI (FD-SOI) process technology. Our proposed SRAM adopts a selective sourceline drive (SSD) scheme and a consecutive data write technique for improving active energy efficiency at low voltage. The novel SSD scheme controls sourceline voltage and eliminates leakage energy at unselected columns in read operations. We fabricated a 64-Kb 8T dual-port SRAM in the 28-nm FD-SOI process technology. The 8T SRAM cell size is <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$0.291 \times 1.457\,\,\mu \text{m}^{2}$ </tex-math></inline-formula> . The test chip exhibits 0.48-V operation at an access time of 135 ns. The energy minimum point is at a supply voltage of 0.56 V and an access time of 35 ns, where 265.0 fJ/cycle in write operations and 389.6 fJ/cycle in read operations are achieved. These factors are, respectively, 30% and 26% smaller than those of the 8T dual-port SRAM with the conventional scheme.
Year
DOI
Venue
2019
10.1109/TCSI.2018.2885536
IEEE Transactions on Circuits and Systems I: Regular Papers
Keywords
Field
DocType
Random access memory,Transistors,Logic gates,Threshold voltage,Switches,MOS devices,Switching circuits
Silicon on insulator,Logic gate,Access time,Voltage,Electronic engineering,Chip,Static random-access memory,Low voltage,Threshold voltage,Mathematics
Journal
Volume
Issue
ISSN
66
4
1549-8328
Citations 
PageRank 
References 
0
0.34
0
Authors
9
Name
Order
Citations
PageRank
Haruki Mori101.35
tomoki nakagawa261.97
yuki kitahara331.27
Yuta Kawamoto401.01
Kenta Takagi5544.42
Shusuke Yoshimoto63012.56
Shintaro Izumi78231.56
Hiroshi Kawaguchi839591.51
masahiko yoshimoto911734.06