Title
Level Shifter Architecture for Dynamically Biasing Ultra-Low Voltage Subcircuits of Integrated Systems
Abstract
Dynamically scaling down the voltage of integrated systems is an effective technique for enabling low-power operation modes. The system is partitioned into several subcircuits, and inactive parts are dynamically biased with low voltages. Additionally, controlling the body bias of subcircuits allows modifying transistor threshold voltages for optimizing speed and power. Both these techniques shift voltages to different levels, demanding dedicated level shifter cells. This paper presents a novel level shifter CMOS architecture able to operate with ultra-low voltages at the expense of reasonable delay and power penalty. Results in technology UTBB FD-SOI 28 nm show the proposed architecture would be controllable by subcircuits of systems operating at 0.19 V, which is lower than the minimum voltage (0.32 V) reachable by the most effective state-of-the-art level shifter cell simulated under the same conditions.
Year
DOI
Venue
2018
10.1109/ISCAS.2018.8351677
2018 IEEE International Symposium on Circuits and Systems (ISCAS)
Keywords
Field
DocType
body bias control,level shifter cells,level shifter CMOS architecture,UTBB FD-SOI technology,ultra-low voltages,transistor threshold voltages,low-power operation modes,integrated systems,dynamically biasing ultra-low voltage subcircuits,level shifter architecture,size 28.0 nm,voltage 0.19 V,Si
Computer science,Voltage,CMOS,Electronic engineering,Integrated systems,Low voltage,Logic level,Transistor,Scaling,Biasing
Conference
ISSN
ISBN
Citations 
0271-4302
978-1-5386-4882-7
1
PageRank 
References 
Authors
0.36
0
6