Name
Abstract | ||
|---|---|---|
Rapid progress in technology scaling has introduced massive parallel computing systems with multiple cores on the integrated circuit (IC), in which a flexible and scalable packet-switched architecture, Network-on-Chip (NoC), is commonly used for communication among the cores. However, technology scaling has also increased the susceptibility to internal defects in such systems. So, manufacturing tests of such multicore systems is crucial and this is a complex and time-consuming process. Due to stress on time-to-market, test engineers focus on the reduction of testtime and perform parallel tests of cores. Due to aggressive technology scaling into the nanometer regime, power consumption is also becoming a significant burden. Moreover, power consumption during manufacturing tests is more as compared to normal operation. In addition, peak power consumption is often significantly higher than the average power values. The consumed power leads to high temperature and creates hotspots, which in turn leads to failure of good parts, resulting in yield loss. Thermal safety during testing is an utmost challenging problem in NoC-based multicore systems, including three-dimensional NoC-based (3D NoC) multicore systems due to stacking of layers. This work proposes a preemptive test scheduling technique for NoC-based multicore systems to reduce the testtime by minimizing conflicts of resource usage. The preemptive test scheduling problem has been formulated using Integer Linear Programming (ILP). In this article, authors have also presented a thermal-aware test scheduling technique to test cores in 2D as well as 3D stacked NoC-based multicore systems using a Particle Swarm Optimization (PSO) based approach. To improve the solution further, several innovative augmentation techniques have been incorporated in the basic PSO. Experimental results highlight the effectiveness of the proposed method in reducing testtime and peak temperature under the power constraints and achieve a tradeoff between testtime and peak temperature.
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Year | DOI | Venue |
|---|---|---|
2019 | 10.1145/3241050 | JETC |
Keywords | Field | DocType |
3D NoC, Network-on-chip (NoC), TSV placement, application mapping | Thermal,Computer science,Test scheduling,Network on a chip,Electronic engineering,Embedded system | Journal |
Volume | Issue | ISSN |
15 | 1 | 1550-4832 |
Citations | PageRank | References |
0 | 0.34 | 35 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Kanchan Manna | 1 | 44 | 5.53 |
| Chatla Swami Sagar | 2 | 0 | 0.34 |
| Santanu Chattopadhyay | 3 | 343 | 44.89 |
| Indranil Sengupta | 4 | 498 | 55.11 |