Name
Abstract | ||
|---|---|---|
A slew-driven clock tree synthesis (SLECTS) methodology is proposed for nanoscale technologies where the interconnect resistance dominates device resistance, thereby increasing the challenge of satisfying the slew constraint. This issue is exacerbated at lower voltages due to degraded drive ability of the clock buffers. A paradigm shift from the traditional delay (and skew)-driven approaches to the proposed slew-driven methodology is therefore required. SLECTS is developed in this paper to satisfy tight slew constraints, which can be costly or infeasible with delay (skew)-driven methodologies and reduce the power dissipation of the clock tree, since the slew and skew constraints are simultaneously and methodically considered. Experimental results performed on an industrial circuit with more than 1M gates designed in 28-nm technology demonstrate that clock power is reduced by approximately 15% as compared to a commercial clock tree synthesis tool under similar slew and skew constraints. |
Year | DOI | Venue |
|---|---|---|
2019 | 10.1109/TVLSI.2018.2888958 | IEEE Transactions on Very Large Scale Integration (VLSI) Systems |
Keywords | Field | DocType |
Merging,Clocks,Microsoft Windows,Delays,Wires,Integrated circuit interconnections,Capacitance | Clock power,Capacitance,Computer science,Dissipation,Voltage,Clock tree,Electronic engineering,Skew,Interconnection,Clock tree synthesis | Journal |
Volume | Issue | ISSN |
27 | 4 | 1063-8210 |
Citations | PageRank | References |
0 | 0.34 | 0 |
Authors | ||
6 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Weicheng Liu | 1 | 3 | 1.77 |
| Can Sitik | 2 | 15 | 3.80 |
| Emre Salman | 3 | 98 | 21.01 |
| Baris Taskin | 4 | 227 | 40.82 |
| Savithri Sundareswaran | 5 | 0 | 0.34 |
| Benjamin Huang | 6 | 0 | 0.34 |