Name
Abstract | ||
|---|---|---|
Asynchronous circuits are inherently more robust than their synchronous counterparts. Desynchronization is a way to obtain asynchronous circuits from a synchronous specification using standard design tools while improving circuit for variation tolerance, electromagnetic interference, and resulting in similar area, delay, and energy as the synchronous baseline. This paper proposes a novel operation-dependent desynchronization technique, which desynchronizes the circuit and improves performance beyond the limits of synchronous design. We perform a case study of our proposed technique on RISC-V rocket core and show significant improvement in performance with minimal power and area overheads. |
Year | DOI | Venue |
|---|---|---|
2019 | 10.1109/TVLSI.2018.2885335 | IEEE Transactions on Very Large Scale Integration (VLSI) Systems |
Keywords | Field | DocType |
Clocks,Pipelines,Delays,Asynchronous circuits,Registers,Delay lines,Standards | Asynchronous communication,Pipeline transport,Computer science,Electromagnetic interference,Electronic engineering,Frequency scaling,Electronic circuit,Rocket | Journal |
Volume | Issue | ISSN |
27 | 4 | 1063-8210 |
Citations | PageRank | References |
0 | 0.34 | 0 |
Authors | ||
2 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Nitish Srivastava | 1 | 0 | 0.34 |
| Rajit Manohar | 2 | 1038 | 96.72 |