Name
Abstract | ||
|---|---|---|
Three-Dimensional NAND flash technology is one of the most competitive integrated solutions for the high-volume massive data storage. So far, there are few investigations on how to use 3-D NAND flash for in-memory computing in the neural network accelerator. In this brief, we propose using the 3-D vertical channel NAND array architecture to implement the vector–matrix multiplication (VMM) with for the first time. Based on the array-level SPICE simulation, the bias condition including the selector layer and the unselected layers is optimized to achieve high computation accuracy of VMM. Since the VMM can be performed layer by layer in a 3-D NAND array, the read-out latency is largely improved compared to the conventional single-cell read-out operation. The impact of device-to-device variation on the computation accuracy is also analyzed. |
Year | DOI | Venue |
|---|---|---|
2019 | 10.1109/TVLSI.2018.2882194 | IEEE Transactions on Very Large Scale Integration (VLSI) Systems |
Keywords | Field | DocType |
Computer architecture,Virtual machine monitors,Resistance,Microprocessors,Transistors,Solid modeling,Logic gates | Logic gate,Computer science,Computer data storage,Spice,Parallel computing,Electronic engineering,NAND gate,Multiplication,Transistor,Matrix multiplication,Computation | Journal |
Volume | Issue | ISSN |
27 | 4 | 1063-8210 |
Citations | PageRank | References |
5 | 0.47 | 0 |
Authors | ||
7 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Panni Wang | 1 | 5 | 0.47 |
| Feng Xu | 2 | 194 | 23.14 |
| Bo Wang | 3 | 7 | 2.89 |
| Gao B | 4 | 44 | 13.39 |
| Huaqiang Wu | 5 | 27 | 11.21 |
| Qian He | 6 | 73 | 13.50 |
| Shimeng Yu | 7 | 490 | 56.22 |