Name
Title | ||
|---|---|---|
A 290-mV, 7-nm Ultra-Low-Voltage One-Port SRAM Compiler Design Using a 12T Write Contention and Read Upset Free Bit-Cell |
Abstract | ||
|---|---|---|
In this paper, we present an ultra-low voltage one-port static random access memory (SRAM) compiler targeting small to medium array sizes to provide a smaller area solution compared to conventional 6T-based SRAMs. A 12T write contention and read upset free bit-cell are used in the design. Array architecture employs a read–modify–write scheme to support bit-write (BW) masking and column multiplexing. Built-in-self-test (BIST) and synchronous write-through (SWT) options are also supported to provide testability features, while power management (PM) option is included to provide low-leakage sleep and shut-down modes. The proposed design is fabricated in 7-nm FinFET technology and achieves the lowest reported
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of 290 mV in this technology. |
Year | DOI | Venue |
|---|---|---|
2019 | 10.1109/JSSC.2019.2895236 | IEEE Journal of Solid-State Circuits |
Keywords | Field | DocType |
Random access memory,Transistors,Latches,Standards,Neural networks,System-on-chip,Layout | Testability,System on a chip,Computer science,Compiler,Static random-access memory,Electronic engineering,Upset,Low voltage,Computer hardware,Multiplexing,Bit cell | Journal |
Volume | Issue | ISSN |
54 | 4 | 0018-9200 |
Citations | PageRank | References |
1 | 0.35 | 0 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Mahmut E. Sinangil | 1 | 70 | 8.03 |
| Yen-Ting Lin | 2 | 5 | 4.11 |
| Hung-Jen Liao | 3 | 61 | 12.94 |
| Jonathan Yung-Cheng Chang | 4 | 166 | 25.48 |