| An 89tops/W And 16.3tops/Mm(2) All-Digital Sram-Based Full-Precision Compute-In Memory Macro In 22nm For Machine-Learning Edge Applications | 1 | 0.35 | 2021 |
| A 7-nm Compute-in-Memory SRAM Macro Supporting Multi-Bit Input, Weight and Output and Achieving 351 TOPS/W and 372.4 GOPS | 3 | 0.41 | 2021 |
| 15.3 A 351tops/W And 372.4gops Compute-In-Memory Sram Macro In 7nm Finfet Cmos For Machine-Learning Applications | 2 | 0.40 | 2020 |
| A 1-Mb 28-nm 1T1MTJ STT-MRAM With Single-Cap Offset-Cancelled Sense Amplifier and <italic>In Situ</italic> Self-Write-Termination | 1 | 0.36 | 2019 |
| A 290-mV, 7-nm Ultra-Low-Voltage One-Port SRAM Compiler Design Using a 12T Write Contention and Read Upset Free Bit-Cell | 1 | 0.35 | 2019 |
| A 290MV Ultra-Low Voltage One-Port SRAM Compiler Design Using a 12T Write Contention and Read Upset Free Bit-Cell in 7NM FinFET Technology | 1 | 0.40 | 2018 |
| Energy-Efficient Reconfigurable SRAM: Reducing Read Power Through Data Statistics. | 0 | 0.34 | 2017 |
| A 28 nm 2 Mbit 6 T SRAM With Highly Configurable Low-Voltage Write-Ability Assist Implementation and Capacitor-Based Sense-Amplifier Input Offset Compensation. | 5 | 0.52 | 2016 |
| Reconfigurable, conditional pre-charge SRAM: Lowering read power by leveraging data statistics | 0 | 0.34 | 2016 |
| A reverse write assist circuit for SRAM dynamic write VMIN tracking using canary SRAMs. | 1 | 0.41 | 2014 |
| An SRAM using output prediction to reduce BL-switching activity and statistically-gated SA for up to 1.9× reduction in energy/access | 7 | 0.78 | 2013 |
| Cost and Coding Efficient Motion Estimation Design Considerations for High Efficiency Video Coding (HEVC) Standard. | 4 | 0.46 | 2013 |
| A 28 nm 0.6 V Low Power DSP for Mobile Applications. | 2 | 0.37 | 2012 |
| A Reconfigurable 8T Ultra-Dynamic Voltage Scalable (U-DVS) SRAM in 65 nm CMOS | 42 | 2.56 | 2009 |
