Name
Abstract | ||
|---|---|---|
Recent research on neural networks has shown a significant advantage in machine learning over traditional algorithms based on handcrafted features and models. Neural networks are now widely adopted in regions like image, speech, and video recognition. But the high computation and storage complexity of neural network inference poses great difficulty on its application. It is difficult for CPU platforms to offer enough computation capacity. GPU platforms are the first choice for neural network processes because of its high computation capacity and easy-to-use development frameworks.
However, FPGA-based neural network inference accelerator is becoming a research topic. With specifically designed hardware, FPGA is the next possible solution to surpass GPU in speed and energy efficiency. Various FPGA-based accelerator designs have been proposed with software and hardware optimization techniques to achieve high speed and energy efficiency. In this article, we give an overview of previous work on neural network inference accelerators based on FPGA and summarize the main techniques used. An investigation from software to hardware, from circuit level to system level is carried out to complete analysis of FPGA-based neural network inference accelerator design and serves as a guide to future work.
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Year | DOI | Venue |
|---|---|---|
2018 | 10.1145/3289185 | TRETS |
Keywords | Field | DocType |
FPGA architecture, neural network, parallel processing | Computer science,Efficient energy use,Inference,Parallel processing,Field-programmable gate array,Real-time computing,Software,Artificial neural network,Computer engineering,Computation,System level | Journal |
Volume | Issue | ISSN |
12 | 1 | 1936-7406 |
Citations | PageRank | References |
19 | 0.93 | 0 |
Authors | ||
5 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Kaiyuan Guo | 1 | 332 | 19.19 |
| Shulin Zeng | 2 | 28 | 4.82 |
| Jincheng Yu | 3 | 315 | 19.49 |
| Yu Wang | 4 | 23 | 3.66 |
| Huazhong Yang | 5 | 2239 | 214.90 |