A Diagnosable Network-on-Chip for FPGA Verification of Intellectual Properties. - Citegraph

Paper Info

Title
A Diagnosable Network-on-Chip for FPGA Verification of Intellectual Properties.

Abstract
Debug and validation are important steps required to ensure that systems-on-chip satisfies the design specs. This article presents an elegant diagnosis technique integrated within the network-on-chip infrastructure. The authors demonstrate the proposed technique on an FPGA prototype.

Year	DOI	Venue
2019	10.1109/MDAT.2018.2890238	IEEE Design & Test
Keywords	Field	DocType
Field programmable gate arrays,Debugging,Monitoring,IP networks,Network-on-chip,System-on-chip,Receivers	Computer science,Field-programmable gate array,FPGA prototype,Network on a chip,Intellectual property,Computer engineering,Embedded system,Debugging	Journal
Volume	Issue	ISSN
36	2	2168-2356
Citations	PageRank	References
0	0.34	0
Authors
4

Authors (4 rows)

Cited by (0 rows)

References (0 rows)

Name	Order	Citations	PageRank
Kyuseung Han	1	58	7.86
Jae-Jin Lee	2	27	8.69
Woojoo Lee	3	104	10.96
Jinho Lee	4	536	47.15

1