| Developing TEI-Aware Ultralow-Power SoC Platforms for IoT End Nodes | 0 | 0.34 | 2021 |
| A Diagnosable Network-on-Chip for FPGA Verification of Intellectual Properties. | 0 | 0.34 | 2019 |
| TEI-ULP: Exploiting Body Biasing to Improve the TEI-Aware Ultra-Low Power Methods | 0 | 0.34 | 2019 |
| TIP: A Temperature Effect Inversion-Aware Ultra-Low Power System-on-Chip Platform | 0 | 0.34 | 2019 |
| MMNoC: Embedding Memory Management Units into Network-on-Chip for Lightweight Embedded Systems. | 0 | 0.34 | 2019 |
| TEI-NoC: Optimizing Ultralow Power NoCs Exploiting the Temperature Effect Inversion. | 1 | 0.37 | 2018 |
| TEI-power: Temperature Effect Inversion-Aware Dynamic Thermal Management. | 1 | 0.37 | 2017 |
| Software-Level Approaches for Tolerating Transient Faults in a Coarse-GrainedReconfigurable Architecture | 3 | 0.38 | 2014 |
| Leveraging parallelism in the presence of control flow on CGRAs | 1 | 0.36 | 2014 |
| Design of a coarse-grained reconfigurable architecture with floating-point support and comparative study | 3 | 0.39 | 2014 |
| Power-Efficient Predication Techniques for Acceleration of Control Flow Execution on CGRA | 12 | 0.63 | 2013 |
| Enhancing Utilization of Integer Functional Units for High-Throughput Floating Point Operations on Coarse-Grained Reconfigurable Architecture. | 0 | 0.34 | 2013 |
| Compiling control-intensive loops for CGRAs with state-based full predication | 12 | 0.61 | 2013 |
| State-based full predication for low power coarse-grained reconfigurable architecture | 9 | 0.60 | 2012 |
| A host-accelerator communication architecture design for efficient binary acceleration | 5 | 1.16 | 2011 |
| Acceleration of control flow on CGRA using advanced predicated execution | 11 | 0.62 | 2010 |
| Coarse-grained reconfigurable architecture for multiple application domains: a case study | 0 | 0.34 | 2009 |
