Name
Abstract | ||
|---|---|---|
Networks-On-Chip (NoCs) have emerged as a promising solution to replace global on-chip interconnections in System-On-Chip (SoC) thanks to better performance and lower power. However, the increasing complexity of NoC routers and the continuous miniaturization of silicon technology are making this interconnection circuit increasingly vulnerable to transient faults. Consequently, during the design and verification phase, an accurate fault injection solution is needed to assess the reliability and behavior of the NoC architecture in the presence of faults. In this paper, a hybrid method that combines FPGA-based and Layout-based fault injection is proposed. This method manipulates the gate netlist provided by the ASIC design flow as well as the FPGA design flow to emulate soft errors in the Networks-on-Chip. Furthermore, the automated fault injection campaign supports the emulation of single faults as well as multiple faults by taking cell adjacency into account. Finally, a case study using two-dimensional NoC is used to validate our methodology. |
Year | DOI | Venue |
|---|---|---|
2019 | 10.1109/LATW.2019.8704559 | 2019 IEEE Latin American Test Symposium (LATS) |
Keywords | Field | DocType |
Fault injection,Network-On-Chip,Multiple bit upset (MBU),multiple event transient (MET),System-On-Chip,FPGA-Flow,ASIC-Flow | Netlist,System on a chip,Computer science,Field-programmable gate array,Network on a chip,Application-specific integrated circuit,Emulation,Interconnection,Fault injection,Embedded system | Conference |
ISBN | Citations | PageRank |
978-1-7281-1756-0 | 0 | 0.34 |
References | Authors | |
0 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Alexandre Coelho | 1 | 3 | 1.16 |
| Nacer-Eddine Zergainoh | 2 | 129 | 19.39 |
| Raoul Velazco | 3 | 124 | 19.48 |