Paper Info
Title
A 28-Nm 75-Fs(Rms) Analog Fractional-N Sampling Pll With A Highly Linear Dtc Incorporating Background Dtc Gain Calibration And Reference Clock Duty Cycle Correction
Abstract
An analog fractional-N sampling phase-locked loop (PLL) is presented. It achieves 75-fs rms jitter, integrated from 10 kHz to 10 MHz, and a -249.7-dB figure of merit (FoM) at the fractional-N mode with a 52-MHz reference clock. The measured fractional spur is less than -64 dBc across the 5.5-7.3-GHz output frequency band. The PLL employs digitalto- time converter (DTC)-based sampling PLL architecture, high linearity DTC design techniques, background DTC gain calibration, and reference clock duty cycle correction (DCC) to improve the integrated phase noise (IPN) and fractional spur. This design meets the performance requirement of the 5G cellular 64-quadratic-amplitude modulation (QAM) standard in the 28-/39-GHz band, supporting 2 x 2 multi-in multi-out (MIMO). This paper, implemented in a 28-nm CMOS process, is integrated in a 5G millimeter-wave cellular transceiver. This PLL consumes 18.9 mW and occupies 0.45 mm(2).
Year
DOI
Venue
2019
10.1109/JSSC.2019.2899726
IEEE JOURNAL OF SOLID-STATE CIRCUITS
Keywords
DocType
Volume
Analog phase-locked loop (PLL), digital-to-time convert (DTC), DTC gain calibration, duty cycle correction (DCC), fractional-N PLL, low jitter, reference clock doubler, sampling phase detector (SPD), voltage-controlled oscillator (VCO)
Journal
54
Issue
ISSN
Citations 
5
0018-9200
0
PageRank 
References 
Authors
0.34
0
11
Name
Order
Citations
PageRank
Wanghua Wu1606.89
Chih-Wei Yao2143.60
Kunal Godbole301.01
Ronghua Ni401.35
Pei-Yuan Chiang500.68
Yongping Han600.68
Yongrong Zuo701.35
Ashutosh Verma801.01
Ivan Siu-Chuang Lu900.34
SangWon Son10224.77
Thomas Byunghak Cho11218.93