Name
Title | ||
|---|---|---|
Voltage-Controlled Magnetoelectric Memory Bit-cell Design With Assisted Body-bias in FD-SOI |
Abstract | ||
|---|---|---|
Voltage-controlled magnetic anisotropy (VCMA)-magnetic tunnel junction (MTJ) is incorporated into FD-SOI CMOS technology. The design space of 1 transistor-1 MTJ (1T-1M) bit-cell is explored through varied VCMA pulse duration/amplitude and scaling down transistor dimensions. The design point with 1.1 V VCMA pulse amplitude, 0.44 ns pulse duration and W/L = 400 nm/30 nm access transistor shows the ultra low write energy in VCMA-MTJ based bit-cell. It achieves a minimum 3.18 fJ/bit switching energy with 28-nm FD-SOI process. Access transistor sizing is studied, while the ultra low power implementation may lead to MTJ switching failure. Voltage assisted techniques for failure mitigation are proposed based on body-bias generator (BBG). The BBG not only provides VCMA pulse signal to control MTJ barrier, but also generates body-bias to boost the transistor performance. In the presence of forward body-bias (FBB) and increased VCMA pulse level, the proposed strategy is effective in switching failure compensation as well as writing delay improvement.
|
Year | DOI | Venue |
|---|---|---|
2019 | 10.1145/3299874.3317982 | Proceedings of the 2019 on Great Lakes Symposium on VLSI |
Keywords | Field | DocType |
design boundary, fd-soi, ultra-low power, vcma-mtj, voltage assisted techniques | Silicon on insulator,Computer science,Voltage,Tunnel junction,Electronic engineering,CMOS,Pulse duration,Transistor,Optoelectronics,Pulse-amplitude modulation,Bit cell | Conference |
ISSN | ISBN | Citations |
1066-1395 | 978-1-4503-6252-8 | 0 |
PageRank | References | Authors |
0.34 | 0 | 7 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Hao Cai | 1 | 11 | 5.27 |
| Menglin Han | 2 | 3 | 2.43 |
| Weiwei Shan | 3 | 22 | 12.51 |
| Jun Yang | 4 | 147 | 36.54 |
| You Wang | 5 | 29 | 9.66 |
| Wang Kang | 6 | 161 | 27.54 |
| Weisheng Zhao | 7 | 730 | 105.43 |