Name
Abstract | ||
|---|---|---|
Malicious circuit modifications known as hardware Trojans represent a rising threat to the integrated circuit supply chain. As many Trojans are activated based on a specific sequence of circuit states, we have recognized the ease of utilizing an instruction sequence for Trojan activation inside a processor core as a significant security issue. To protect against this threat, we propose Control-Lock: a novel methodology for securing inter-module control signals against software-controlled hardware Trojans, even if the signals are known to the adversary during fabrication. We demonstrate the approach with a RISC-V processor infected with a denial of service Trojan. We evaluate different Control-Lock encryption schemes with regards to the security-cost trade-off. Our results show that protecting a processor against a software-controlled hardware Trojan exploiting code execution implies an area overhead of only 4.75% as well as a negligible delay and power overhead.
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Year | DOI | Venue |
|---|---|---|
2019 | 10.1145/3299874.3317983 | Proceedings of the 2019 on Great Lakes Symposium on VLSI |
Keywords | Field | DocType |
denial of service, hardware trojans, logic encryption, risc-v | RISC-V,Hardware Trojan,Denial-of-service attack,Computer science,Encryption,Software,Computer hardware,Trojan,Multi-core processor,Integrated circuit | Conference |
ISSN | ISBN | Citations |
1066-1395 | 978-1-4503-6252-8 | 2 |
PageRank | References | Authors |
0.41 | 0 | 5 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Dominik Sisejkovic | 1 | 11 | 5.06 |
| Farhad Merchant | 2 | 56 | 10.68 |
| Rainer Leupers | 3 | 1389 | 136.48 |
| G. Ascheid | 4 | 230 | 57.65 |
| Sascha Kegreiss | 5 | 2 | 0.74 |