| Deceptive Logic Locking for Hardware Integrity Protection Against Machine Learning Attacks | 0 | 0.34 | 2022 |
| PA-PUF: A Novel Priority Arbiter PUF | 0 | 0.34 | 2022 |
| NISTT: A Non-Intrusive SystemC-TLM 2.0 Tracing Tool | 0 | 0.34 | 2022 |
| Design and Exploration of an ARC-Coprocessor for LSTM Based Audio Applications | 0 | 0.34 | 2022 |
| AMAIX In-Depth: A Generic Analytical Model for Deep Learning Accelerators | 0 | 0.34 | 2022 |
| ConvAix: An Application-Specific Instruction-Set Processor for the Efficient Acceleration of CNNs | 1 | 0.43 | 2021 |
| An Investigation on Inherent Robustness of Posit Data Representation | 1 | 0.35 | 2021 |
| Bridging the Frequency Gap in Heterogeneous 3D SoCs through Technology-Specific NoC Router Architectures | 0 | 0.34 | 2021 |
| Challenging the Security of Logic Locking Schemes in the Era of Deep Learning: A Neuroevolutionary Approach | 3 | 0.40 | 2021 |
| QFlow: Quantitative Information Flow for Security-Aware Hardware Design in Verilog | 1 | 0.35 | 2021 |
| Logic Locking at the Frontiers of Machine Learning: A Survey on Developments and Opportunities | 0 | 0.34 | 2021 |
| Modelling Machine Learning Components for Mapping and Scheduling of AUTOSAR Runnables | 0 | 0.34 | 2020 |
| 3D Optimisation of Software Application Mappings on Heterogeneous MPSoCs. | 0 | 0.34 | 2020 |
| Multi-objective optimisation of software application mappings on heterogeneous MPSoCs: TONPET versus R2-EMOA. | 0 | 0.34 | 2019 |
| Fast SystemC Processor Models with Unicorn | 2 | 0.40 | 2019 |
| A heuristic for multi objective software application mappings on heterogeneous MPSoCs. | 2 | 0.42 | 2019 |
| Control-Lock: Securing Processor Cores Against Software-Controlled Hardware Trojans | 2 | 0.41 | 2019 |
| Inter-Lock: Logic Encryption for Processor Cores Beyond Module Boundaries | 0 | 0.34 | 2019 |
| Efficient Realization of Givens Rotation through Algorithm-Architecture Co-design for Acceleration of QR Factorization. | 0 | 0.34 | 2018 |
| AMVP - a high performance virtual platform using parallel systemC for multicore ARM architectures: work-in-progress | 0 | 0.34 | 2018 |
| Multi-Scale Code Generation for Simulation-Driven Rapid ADAS Prototyping: the SMELT Approach | 0 | 0.34 | 2018 |
| Fully Virtual Rapid ADAS Prototyping via a Joined Multi-domain Co-simulation Ecosystem. | 0 | 0.34 | 2018 |
| OHEX: OS-aware hybridization techniques for accelerating MPSoC full-system simulation | 0 | 0.34 | 2018 |
| Vlsi Implementation Of Ls-Svm Training And Classification Using Entropy Based Subset-Selection | 0 | 0.34 | 2017 |
| Towards Parallelism Extraction for Heterogeneous Multicore Android Devices. | 1 | 0.41 | 2017 |
| Black box ESL power estimation for loosely-timed TLM models | 0 | 0.34 | 2016 |
| Black Box Power Estimation For Digital Signal Processors Using Virtual Platforms | 3 | 0.40 | 2016 |
| Dynamic Many-process Applications on Many-tile Embedded Systems and HPC Clusters: the EURETILE programming environment and execution platforms | 5 | 0.52 | 2016 |
| Automatic parallelization and accelerator offloading for embedded applications on heterogeneous MPSoCs. | 5 | 0.48 | 2016 |
| Frequency-Aware ESL Power Estimation for ARM Cortex-A9 Using a Black Box Processor Model. | 2 | 0.38 | 2016 |
| Enhanced GPU Resource Utilization through Fairness-aware Task Scheduling | 1 | 0.35 | 2015 |
| A comparative investigation of device-specific mechanisms for exploiting HPC accelerators | 0 | 0.34 | 2015 |
| Application-Specific Architecture Exploration Based on Processor-Agnostic Performance Estimation | 0 | 0.34 | 2015 |
| Extraction of Kahn Process Networks from While Loops in Embedded Software | 0 | 0.34 | 2015 |
| Deterministic event-based control of Virtual Platforms for MPSoC software debugging | 0 | 0.34 | 2015 |
| Parallelism extraction in embedded software for android devices | 4 | 0.71 | 2015 |
| Automatic detection of concurrency bugs through event ordering constraints | 6 | 0.46 | 2014 |
| VLSI design of a parallel MCMC-based MIMO detector with multiplier-free Gibbs samplers | 5 | 0.73 | 2014 |
| VLSI implementation of linear MIMO detection with boosted communications performance: extended abstract | 1 | 0.38 | 2014 |
| Pre-architectural performance estimation for ASIP design based on abstract processor models | 5 | 0.58 | 2014 |
| Energy-efficiency of floating-point and fixed-point SIMD cores for MIMO processing systems | 0 | 0.34 | 2014 |
| Efficient VLSI architectures for matrix inversion in soft-input soft-output MMSE MIMO detectors | 4 | 0.54 | 2014 |
| Improving ESL power models using switching activity information from timed functional models | 2 | 0.37 | 2014 |
| Technology transfer towards horizon 2020 | 2 | 0.45 | 2014 |
| Technology transfer towards horizon 2020 | 2 | 0.45 | 2014 |
| Creation of ESL power models for communication architectures using automatic calibration | 18 | 0.89 | 2013 |
| A compiler infrastructure for embedded heterogeneous MPSoCs | 6 | 0.62 | 2013 |
| Efficient Implementation of Application-Aware Spinlock Control in MPSoCs. | 0 | 0.34 | 2013 |
| MAPS: Mapping Concurrent Dataflow Applications to Heterogeneous MPSoCs. | 33 | 1.09 | 2013 |
| Embedded Real-Time Application Prototyping Using A Hybrid Multiprocessing Platform | 0 | 0.34 | 2013 |
