Name
Abstract | ||
|---|---|---|
This paper introduces a study on miniaturizing on-chip RF inductors using the Slow Wave Transmission Line (SWTL) technique. The inductance of different SWTLs is calculated, simulated, fabricated and measured. The lines are treated as two-port networks where their S-parameters and ABCD parameters are extracted, from which their self-inductance is determined. The simulated results have shown a significant reduction in the coplanar microstrip transmission line length reaching 73% with a constant inductance, characteristic impedance, and electrical length. The idea was validated practically by implementing different SWTLs using CMOS 130nm process. The measured and simulated lines are compared and they have shown matched results. Practically the length reduction has reached 30% due to the constraints imposed by the process design rules on the design. |
Year | DOI | Venue |
|---|---|---|
2018 | 10.1109/mwscas.2018.8624102 | Midwest Symposium on Circuits and Systems Conference Proceedings |
Field | DocType | ISSN |
Wafer,Inductance,Transmission line,Computer science,Inductor,Characteristic impedance,Electrical length,Electronic engineering,CMOS,Process design | Conference | 1548-3746 |
Citations | PageRank | References |
0 | 0.34 | 0 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Ahmad Eldahshan | 1 | 0 | 0.34 |
| William Knisely | 2 | 0 | 0.34 |
| Rony E. Amaya | 3 | 8 | 5.44 |
| Calvin Plett | 4 | 134 | 20.84 |