Name
Abstract | ||
|---|---|---|
A highly linear SAR-VCO MASH delta-sigma ADC architecture is presented. OTA based analog integrators are not needed whereby the ADC is mostly digital and process scaling friendly. A new technique is introduced to extract the quantization noise of the VCO-based quantizer as a PWM signal using digital circuitry. This technique is independent of the OSR and the input signal amplitude of the VCO-based quantizer making it attractive for higher bandwidth applications. The proposed technique is demonstrated with a 0-1-1 MASH delta sigma architecture. Behavioral simulations show second order noise shaping with 75dB SNDR for an OSR of 20. |
Year | DOI | Venue |
|---|---|---|
2018 | 10.1109/mwscas.2018.8623894 | Midwest Symposium on Circuits and Systems Conference Proceedings |
Keywords | Field | DocType |
Analog-to-digital converter (ADC),quantization noise,phase domain,successive-approximation register (SAR) ADC,delta sigma modulator,MASH,PWM generator,nonlinearity,VCO-based quantizer | Time domain,Computer science,Pulse-width modulation,Integrator,Voltage-controlled oscillator,Delta-sigma modulation,Electronic engineering,Noise shaping,Bandwidth (signal processing),Quantization (signal processing) | Conference |
ISSN | Citations | PageRank |
1548-3746 | 0 | 0.34 |
References | Authors | |
0 | 6 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Hamidreza Maghami | 1 | 0 | 1.01 |
| Hossein Mirzaie | 2 | 3 | 2.49 |
| Pedram Payandehnia | 3 | 8 | 5.51 |
| Kartikeya Mayaram | 4 | 349 | 58.50 |
| Ramin Zanbaghi | 5 | 19 | 5.18 |
| Terri S. Fiez | 6 | 167 | 47.25 |