Name
Abstract | ||
|---|---|---|
This work presents 32-phase analog delay-locked-loop (DLL) having fast locking ability, startup-circuit free operation, and a low area with improved DNL-INL performance. The proposed faster delay-cell and the new bias-circuit enable startup-circuit free operation under process-voltage-temperature (PVT) variation, while the DLL achieves low area and faster locking by using a small filter capacitor. Again, input and output clocks pass through the respective CMOS buffer before the phase detector (PD) for load matching, which reduces DNL-INL in the DLL. The analog DLL locks in less than 54 or 56 clock cycles depending upon initial control voltage (supply or ground voltage) with 100 MHz input clock. The DLL generates 32-phase clocks with a bin-size of 312.5 ps, the peak-to-peak period jitter of 9.51 ps, the rms period jitter of 1.36 ps, the phase-offset error of 4.72 ps, DNL and INL less than ±0.11 LSB. The design consumes 3.54 mW power with a supply voltage of 3.3 V, and an area of 0.017 mm2 in UMC 180 nm MMRF technology. © 2001 Elsevier Science. All rights reserved |
Year | DOI | Venue |
|---|---|---|
2019 | 10.1016/j.vlsi.2019.01.003 | Integration |
Keywords | Field | DocType |
Bin-size,Complementary metal oxide semiconductor (CMOS),Delay-cell,Delay-locked-loop (DLL),Differential non linearity (DNL),Integral non linearity (INL),Phase detector (PD),Process voltage temperature (PVT),True single phase clock (TSPC) | Load balancing (electrical power),Filter capacitor,Computer science,Voltage,Electronic engineering,CMOS,Input/output,Phase detector,Jitter,Least significant bit | Journal |
Volume | ISSN | Citations |
66 | 0167-9260 | 0 |
PageRank | References | Authors |
0.34 | 0 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Sabir Ali Mondal | 1 | 0 | 0.68 |
| Pradip Mandal | 2 | 84 | 23.04 |
| Hafizur Rahaman | 3 | 368 | 91.37 |