Paper Info
Title
Design and Evaluation of a 28-nm FD-SOI STT-MRAM for Ultra-Low Power microcontrollers
Abstract
The complexity of embedded devices increases as today's applications request always more services. However, the power consumption of systems-on-chip has significantly increased due to the high-density integration and the high leakage power of current CMOS transistors. To address these issues, emerging technologies are considered. Spin-transfer torque magnetic random access memory (STT-MRAM) is seen as a promising alternative solution to traditional memories, thanks to its negligible leakage current, high density, and non-volatility. In this paper, we present the design and evaluation of a 128-kB STT-RAM in a 28-nm FD-SOI technology with SRAM-like interface for ultra-low power microcontrollers. With 0.9-pJ/bit read in 5 ns and 3-pJ/bit write in 10 ns, this embedded non-volatile memory is suitable for the devices that run at frequencies under 100 MHz. Considering a low-power application with duty-cycled behavior, we evaluate the STT-MRAM as a replacement of embedded Flash and SRAM by comparing single- and multi-memory architecture scenarios.
Year
DOI
Venue
2019
10.1109/ACCESS.2019.2906942
IEEE ACCESS
Keywords
Field
DocType
28-nm FD-SOI,microcontroller,STT-MRAM,ultra-low-power
Silicon on insulator,Leakage (electronics),Computer science,Static random-access memory,Magnetoresistive random-access memory,CMOS,Microcontroller,Transistor,Electrical engineering,Distributed computing,Random access
Journal
Volume
ISSN
Citations 
7
2169-3536
0
PageRank 
References 
Authors
0.34
0
6
Name
Order
Citations
PageRank
Guillaume Patrigeon142.52
P. Benoit27412.39
Lionel Torres334653.92
Sophiane Senni4226.06
Guillaume Prenat58013.62
Gregory Di Pendina6337.27