Name
Playground
About
FAQ
GitHub
Playground
Shortest Path Finder
Community Detector
Connected Papers
Author Trending
Luca Galli
Claudia Calabrese
Hao Mao
Ning Wang
Peter Malec
Giovanni Venturelli
Chen Ma
Radu Timofte
Kuanrui Yin
Francisco J. Rodriguez
Home
/
Author
/
GUILLAUME PRENAT
Author Info
Open Visualization
Name
Affiliation
Papers
GUILLAUME PRENAT
CEA, CNRS, SPINTEC Lab, Grenoble, France
22
Collaborators
Citations
PageRank
86
80
13.62
Referers
Referees
References
207
279
98
Search Limit
100
279
Publications (22 rows)
Collaborators (86 rows)
Referers (100 rows)
Referees (100 rows)
Title
Citations
PageRank
Year
A Universal Spintronic Technology based on Multifunctional Standardized Stack
1
0.37
2020
Design and Evaluation of a 28-nm FD-SOI STT-MRAM for Ultra-Low Power microcontrollers
0
0.34
2019
From Spintronic Devices to Hybrid CMOS/Magnetic System On Chip
0
0.34
2018
Resistive and Spintronic RAMs: Device, Simulation, and Applications
0
0.34
2018
Using Multifunctional Standardized Stack As Universal Spintronic Technology For Iot
1
0.35
2018
MRAM - from STT to SOT, for security and memory.
1
0.35
2018
GREAT: HeteroGeneous IntegRated Magnetic tEchnology Using Multifunctional Standardized sTack
1
0.40
2017
Ultra-Fast and High-Reliability SOT-MRAM: From Cache Replacement to Normally-Off Computing.
11
1.06
2016
Multi-context non-volatile content addressable memory using magnetic tunnel junctions
0
0.34
2016
Reducing System Power Consumption Using Check-Pointing on Nonvolatile Embedded Magnetic Random Access Memories.
2
0.39
2016
Robust magnetic full-adder with voltage sensing 2T/2MTJ cell
0
0.34
2015
Synchronous 8-bit Non-Volatile Full-Adder based on Spin Transfer Torque Magnetic Tunnel Junction
11
0.64
2015
Hybrid CMOS/magnetic Process Design Kit and SOT-based non-volatile standard cell architectures
0
0.34
2014
Non-volatile FPGAs based on spintronic devices
6
0.58
2013
Emerging hybrid logic circuits based on non-volatile magnetic memories
1
0.40
2013
Hybrid CMOS/magnetic process design kit and application to the design of high-performances non-volatile logic circuits
1
0.36
2011
Ultra compact non-volatile flip-flop for low power digital circuits based on hybrid CMOS/magnetic technology
4
0.54
2011
TAS-MRAM-Based Low-Power High-Speed Runtime Reconfiguration (RTR) FPGA
13
1.65
2009
CMOS/Magnetic Hybrid Architectures
8
1.27
2007
Tas-Mram Based Non-Volatile Fpga Logic Circuit
17
2.43
2007
A low-cost digital frequency testing approach for mixed-signal devices using SigmaDelta modulation
0
0.34
2005
A 0.18 μm CMOS implementation of on-chip analogue test signal generation from digital test patterns
2
0.46
2004
1
