Paper Info
Title
MTTF Enhancement Power-C4 Bump Placement Optimization
Abstract
Constructing a reliable power delivery network (PDN) is increasingly challenging by further technology scaling. PDN suffers from long-term reliability threats such as electromigration (EM). EM results in permanent failures and directly affects chip lifetime and voltage stability. Loss of limited controlled collapse chip connection (C4) pads to EM makes delivering a stable supply voltage more critical. The C4 bumps failure mechanism depends on current density, on-chip voltage noise, and temperature. In this paper, we develop a statistical simulation framework to analyze the effect of accurate chip temperature on multiple power-bump wearout. Our result shows that using uniform temperature leads, in the pessimistic system, to mean-time-to-failure (MTTF). Meanwhile, the current C4 pad placement optimization algorithms consider the current source or voltage drop as the forces to move the pads that do not lead to maximum MTTF. We propose a new technique to improve the efficiency of optimization algorithms by exploring the temperature as a new virtual force to move the pads. Experimental results show that our algorithm improves the MTTF by 25.43% that will support more off-chip I/O channels in current and near-future technology nodes.
Year
DOI
Venue
2019
10.1109/tvlsi.2019.2904048
IEEE Transactions on Very Large Scale Integration Systems
Keywords
Field
DocType
Current density,Mathematical model,System-on-chip,Optimization,Reliability,Temperature distribution,Thermal analysis
Mean time between failures,Flip chip,System on a chip,Current source,Computer science,Voltage,Voltage drop,Electronic engineering,Chip,Electromigration
Journal
Volume
Issue
ISSN
27
7
1063-8210
Citations 
PageRank 
References 
0
0.34
0
Authors
6
Name
Order
Citations
PageRank
somayeh rahimipour131.06
Runjie Zhang2455.01
Ke Wang316010.89
Kevin Skadron46188384.18
Fakhrul Z. Rokhani5359.25
Mircea Stan6154.59