Paper Info
Title
DR Refresh: Releasing DRAM Potential by Enabling Read Accesses under Refresh
Abstract
Emerging data analytic workloads such as graph processing, neural network and edge data preprocesing desire efficient memory read operations. Unfortunately, due to the necessity of dynamic refresh, modern DRAM systems have to stall access during refresh cycles. As DRAM device density continues to grow, refresh operations can be a crucial throughput bottleneck. To fully unleash memory access performance, we revisit conventional refresh mechanism and DRAM architecture. We propose DR refresh, a specific refresh mechanism that enable read and refresh operations to be done simultaneously. We devise DR DRAM, a specific memory hardware system that can efficiently deploy DR refresh. Unlike traditional refresh, DR explores device refresh that only refreshes a designated device at a time. Meanwhile, DR increases read efficiency by recovering the inaccessible data that resides on a device under refreshing. We also propose Hybrid Refresh Main Memory (HRMM) which can designate refresh schemes (DR or traditional refresh) in a specific memory space. We expect that our design can benefit many real-life tasks such as SPEC CPU2006, CNN, LLT and PageRank.
Year
DOI
Venue
2019
10.1109/tc.2019.2914679
IEEE Transactions on Computers
Keywords
Field
DocType
Random access memory,Memory management,Bandwidth,Performance evaluation,Magnetic resonance imaging,Throughput,Task analysis
Dram,Bottleneck,Graph,Computer science,Real-time computing,Bandwidth (signal processing),Memory management,Throughput,Spec#,Embedded system
Journal
Volume
Issue
ISSN
68
11
0018-9340
Citations 
PageRank 
References 
0
0.34
0
Authors
9
Name
Order
Citations
PageRank
Yuhai Cao100.34
Chao Li234437.85
Jing Wang36010.89
Weigong Zhang48815.79
Quan Chen5454.05
Jingwen Leng64912.97
Bin Yao736532.71
Yao Shen816422.36
Minyi Guo93969332.25