Jingwen Leng - Citegraph

Author Info

Name	Affiliation	Papers
JINGWEN LENG	Univ Texas Austin, Dept Elect & Comp Engn, Austin, TX 78712 USA	36
Collaborators	Citations	PageRank
98	49	12.97
Referers	Referees	References
171	701	208

Search Limit

100701

Publications (36 rows)

Collaborators (98 rows)

Referers (100 rows)

Referees (100 rows)

Title	Citations	PageRank	Year
SALO: an efficient spatial accelerator enabling hybrid sparse attention mechanisms for long sequences	0	0.34	2022
Transkimmer: Transformer Learns to Layer-wise Skim	1	0.35	2022
PAME: precision-aware multi-exit DNN serving for reducing latencies of batched inferences	0	0.34	2022
SQuant: On-the-Fly Data-Free Quantization via Diagonal Hessian Approximation	0	0.34	2022
Tacker: Tensor-CUDA Core Kernel Fusion for Improving the GPU Utilization while Ensuring QoS	0	0.34	2022
Block-Skim: Efficient Question Answering for Transformer.	0	0.34	2022
ANT: Exploiting Adaptive Numerical Data Type for Low-bit Deep Neural Network Quantization	0	0.34	2022
Dual-side Sparse Tensor Core	5	0.41	2021
Exploiting Intra-SM Parallelism in GPUs via Persistent and Elastic Blocks	1	0.38	2021
AlphaR: Learning-Powered Resource Management for Irregular, Dynamic Microservice Graph	1	0.35	2021
System-level Early-stage Modeling and Evaluation of IVR-assisted Processor Power Delivery System	0	0.34	2021
Predictive Guardbanding: Program-Driven Timing Margin Reduction for GPUs	1	0.39	2021
Enable simultaneous DNN services based on deterministic operator overlap and precise latency prediction	1	0.35	2021
Erratum to “Predictive Guardbanding: Program-Driven Timing Margin Reduction for GPUs”	0	0.34	2021
How Far Does BERT Look At:Distance-based Clustering and Analysis of BERT\'s Attention	0	0.34	2020
Probabilistic robust regression with adaptive weights - a case study on face recognition.	0	0.34	2020
URSA - Precise Capacity Planning and Fair Scheduling based on Low-level Statistics for Public Clouds.	2	0.36	2020
Asymmetric Resilience: Exploiting Task-Level Idempotency for Transient Error Recovery in Accelerator-Based Systems	3	0.35	2020
Sturgeon: Preference-aware Co-location for Improving Utilization of Power Constrained Computers	1	0.35	2020
Balancing Efficiency and Flexibility for DNN Acceleration via Temporal GPU-Systolic Array Integration	1	0.35	2020
Ptolemy: Architecture Support for Robust Deep Learning	1	0.35	2020
CODA: Improving Resource Utilization by Slimming and Co-locating DNN and CPU Jobs	1	0.35	2020
DLFusion: An Auto-Tuning Compiler for Layer Fusion on Deep Neural Network Accelerator	0	0.34	2020
Survey and design of paleozoic: a high-performance compiler tool chain for deep learning inference accelerator.	0	0.34	2020
Accelerating sparse DNN models without hardware-support via tile-wise sparsity	0	0.34	2020
Predicting and reining in application-level slowdown on spatial multitasking GPUs	3	0.38	2020
Avalon: towards QoS awareness and improved utilization through multi-resource management in datacenters	3	0.36	2019
DR Refresh: Releasing DRAM Potential by Enabling Read Accesses under Refresh	0	0.34	2019
Adversarial Defense Through Network Profiling Based Path Extraction	2	0.36	2019
Characterizing Perception Module Performance and Robustness in Production-Scale Autonomous Driving System.	2	0.43	2019
Ebird: Elastic Batch for Improving Responsiveness and Throughput of Deep Learning Services	3	0.43	2019
Themis: Predicting And Reining In Application-Level Slowdown On Spatial Multitasking Gpus	1	0.34	2019
DR DRAM: Accelerating Memory-Read-Intensive Applications	0	0.34	2018
Ivory: Early-Stage Design Space Exploration Tool for Integrated Voltage Regulators.	0	0.34	2017
GPU voltage noise: Characterization and hierarchical smoothing of spatial and temporal voltage noise interference in GPU architectures	12	0.50	2015
Exploiting Webpage Characteristics for Energy-Efficient Mobile Web Browsing	4	0.42	2014