Name
Abstract | ||
|---|---|---|
Today's rapid progress in the physical implementation of quantum computers demands scalable synthesis methods to map practical logic designs to quantum architectures. There exist many quantum algorithms which use classical functions with superposition of states. Motivated by recent trends, in this paper, we show the design of quantum circuit to perform modular exponentiation functions using two different approaches. In the design phase, first we generate quantum circuit from a verilog implementation of exponentiation functions using synthesis tools and then apply two different Quantum Error Correction techniques. Finally the circuit is further optimized using the Linear Nearest Neighbor (LNN) Property. We demonstrate the effectiveness of our approach by generating a set of networks for the reversible modular exponentiation function for a set of input values. At the end of the work, we have summarized the obtained results, where a cost analysis over our developed approaches has been made. Experimental results show that depending on the choice of different QECC methods the performance figures can vary by up to 11%, 10%, 8% in T-count, number of qubits, number of gates respectively. |
Year | DOI | Venue |
|---|---|---|
2019 | 10.1109/VLSID.2019.00088 | 2019 32nd International Conference on VLSI Design and 2019 18th International Conference on Embedded Systems (VLSID) |
Keywords | Field | DocType |
Quantum Algorithm(QA),Modular Exponentiation,Quantum Error Correcting Codes (QECC),Linear Nearest Neighbor (LNN) | Quantum,Computer science,Electronic engineering,Computational science,Electronic circuit,Modular exponentiation | Conference |
ISSN | ISBN | Citations |
1063-9667 | 978-1-7281-0410-2 | 0 |
PageRank | References | Authors |
0.34 | 7 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Rakesh Das | 1 | 6 | 1.66 |
| Anupam Chattopadhyay | 2 | 318 | 62.76 |
| Hafizur Rahaman | 3 | 368 | 91.37 |