Paper Info
Title
SiPterposer: A Fault-Tolerant Substrate for Flexible System-in-Package Design
Abstract
As Moore's Law scaling slows down, specialized heterogeneous designs are needed to sustain computing performance improvements. Unfortunately, the non-recurring engineering (NRE) costs of chip design-designing interconnects, creating masks, etc.-are often prohibitive. Chiplet-based disintegrated design solutions could address these economic issues, but current technologies lack the flexibility to express a rich variety of designs without redesigning the communication substrate. Moreover, as the number of chiplets increases, yield suffers due to 2.5D assembly defects. This work addresses these problems by presenting a flexible communication fabric that supports construction of arbitrary network topologies and provides robust fault-tolerance, demonstrating near-100% chip assembly yield at typical bonding defect rates. We achieve these goals with less than 3% additional power and zero exposed latency overhead for various real-world applications running on an example SiP.
Year
DOI
Venue
2019
10.23919/DATE.2019.8714998
2019 Design, Automation & Test in Europe Conference & Exhibition (DATE)
Keywords
Field
DocType
chip design,chip assembly yield,flexible communication fabric,2.5D assembly defects,communication substrate,current technologies,economic issues,chiplet-based disintegrated design solutions,computing performance improvements,specialized heterogeneous designs,Moore's Law scaling,system-in-package design,fault-tolerant substrate,robust fault-tolerance
System in package,Computer science,Parallel computing,Fault tolerance,Embedded system
Conference
ISSN
ISBN
Citations 
1530-1591
978-1-7281-0331-0
0
PageRank 
References 
Authors
0.34
0
3
Name
Order
Citations
PageRank
Pete Ehrett101.35
Todd M. Austin2384.71
Valeria Bertacco3136586.93