Name
Abstract | ||
|---|---|---|
RISC-V is an open-source instruction set architecture (ISA) with a modular design consisting of a mandatory base part plus optional extensions. The RISC-V 32IMFC ISA configuration has been widely adopted for the design of new-generation, low-power processors. Motivated by the important energy savings that smaller-than-32-bit FP types have enabled in several application domains and related compute platforms, some recent studies have published encouraging early results for their adoption in RISC-V processors. In this paper we introduce a set of ISA extensions for RISC-V 32IMFC, supporting scalar and SIMD operations (fitting the 32-bit register size) for 8-bit and two 16-bit FP types. The proposed extensions are enabled by exposing the new FP types to the standard C/C++ type system and an implementation for the RISC-V GCC compiler is presented. As a further, novel contribution, we extensively characterize the performance and energy savings achievable with the proposed extensions. On average, experimental results show that their adoption provide benefits in terms of performance (1.64x speedup for 16-bit and 2.18x for 8-bit types) and energy consumption (30% saving for 16-bit and 50% for 8-bit types). We also illustrate an approach based on automatic precision tuning to make effective use of the new FP types. |
Year | DOI | Venue |
|---|---|---|
2019 | 10.23919/DATE.2019.8714897 | 2019 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION (DATE) |
Field | DocType | ISSN |
RISC-V,Computer science,Instruction set,Parallel computing,Scalar (physics),SIMD,Compiler,Modular design,Energy consumption,Speedup | Conference | 1530-1591 |
Citations | PageRank | References |
0 | 0.34 | 0 |
Authors | ||
5 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Giuseppe Tagliavini | 1 | 71 | 9.36 |
| Stefan Mach | 2 | 15 | 2.83 |
| Davide Rossi | 3 | 416 | 47.47 |
| Andrea Marongiu | 4 | 337 | 39.19 |
| Luca Benini | 5 | 13116 | 1188.49 |