Name
Abstract | ||
|---|---|---|
Placement for very-large-scale integrated (VLSI) circuits is one of the most important steps for design closure. This paper proposes a novel GPU-accelerated placement framework DREAMPlace, by casting the analytical placement problem equivalently to training a neural network. Implemented on top of a widely-adopted deep learning toolkit PyTorch, with customized key kernels for wirelength and density computations, DREAMPlace can achieve over 30× speedup in global placement without quality degradation compared to the state-of-the-art multi-threaded placer RePlAce. We believe this work shall open up new directions for revisiting classical EDA problems with advancement in AI hardware and software.
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Year | DOI | Venue |
|---|---|---|
2019 | 10.1145/3316781.3317803 | Proceedings of the 56th Annual Design Automation Conference 2019 |
DocType | ISBN | Citations |
Conference | 978-1-4503-6725-7 | 2 |
PageRank | References | Authors |
0.58 | 0 | 6 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Yibo Lin | 1 | 119 | 20.98 |
| Shounak Dhar | 2 | 32 | 4.84 |
| Wuxi Li | 3 | 36 | 6.03 |
| Haoxing Ren | 4 | 288 | 22.61 |
| Brucek Khailany | 5 | 1187 | 118.43 |
| David Z. Pan | 6 | 2653 | 237.64 |