| MAVIREC - ML-Aided Vectored IR-Drop Estimation and Classification. | 0 | 0.34 | 2021 |
| 2021 ICCAD CAD Contest Problem C: GPU Accelerated Logic Rewriting | 0 | 0.34 | 2021 |
| DREAMPlace: Deep Learning Toolkit-Enabled GPU Acceleration for Modern VLSI Placement | 6 | 0.44 | 2021 |
| Optimizing VLSI Implementation with Reinforcement Learning - ICCAD Special Session Paper | 0 | 0.34 | 2021 |
| Invited-NVCe11: Standard Cell Layout in Advanced Technology Nodes with Reinforcement Learning | 0 | 0.34 | 2021 |
| Parasitic-Aware Analog Circuit Sizing with Graph Neural Networks and Bayesian Optimization. | 0 | 0.34 | 2021 |
| Standard Cell Routing with Reinforcement Learning and Genetic Algorithm in Advanced Technology Nodes | 1 | 0.37 | 2021 |
| Problem C: GPU Accelerated Logic Re-simulation : (Invited Talk) | 0 | 0.34 | 2020 |
| Paragraph: Layout Parasitics And Device Parameter Prediction Using Graph Neural Networks | 0 | 0.34 | 2020 |
| ABCDPlace: Accelerated Batch-Based Concurrent Detailed Placement on Multithreaded CPUs and GPUs | 4 | 0.43 | 2020 |
| Accelerating Chip Design With Machine Learning | 1 | 0.37 | 2020 |
| ML for CAD - Where is the Treasure Hiding? | 0 | 0.34 | 2020 |
| GRANNITE: Graph Neural Network Inference for Transferable Power Estimation | 4 | 0.40 | 2020 |
| FIST: A Feature-Importance Sampling and Tree-Based Method for Automatic Design Flow Parameter Tuning | 1 | 0.35 | 2020 |
| Opportunities for RTL and Gate Level Simulation using GPUs (Invited Talk). | 0 | 0.34 | 2020 |
| PowerNet: Transferable Dynamic IR Drop Estimation via Maximum Convolutional Neural Network | 3 | 0.39 | 2020 |
| Toward Intelligent Physical Design - Deep Learning and GPU Acceleration. | 0 | 0.34 | 2019 |
| High Performance Graph Convolutional Networks with Applications in Testability Analysis | 8 | 0.64 | 2019 |
| DREAMPlace: Deep Learning Toolkit-Enabled GPU Acceleration for Modern VLSI Placement | 2 | 0.58 | 2019 |
| Routability-Driven Macro Placement with Embedded CNN-Based Prediction Model | 1 | 0.37 | 2019 |
| PRIMAL: Power Inference using Machine Learning | 5 | 0.40 | 2019 |
| A brief introduction on contemporary High-Level Synthesis | 3 | 0.46 | 2014 |
| Network flow based datapath bit slicing | 7 | 0.54 | 2013 |
| LatchPlanner: Latch placement algorithm for datapath-oriented high-performance VLSI designs | 6 | 0.51 | 2013 |
| Intuitive ECO synthesis for high performance circuits | 4 | 0.45 | 2013 |
| Design methodology for the IBM POWER7 microprocessor | 10 | 0.91 | 2011 |
| Logical and physical restructuring of fan-in trees | 5 | 0.54 | 2010 |
| History-based VLSI legalization using network flow | 20 | 0.85 | 2010 |
| DeltaSyn: an efficient logic difference optimizer for ECO synthesis | 27 | 1.23 | 2009 |
| Low Cost Test Point Insertion Without Using Extra Registers For High Performance Design | 9 | 0.57 | 2009 |
| Techniques for Fast Physical Synthesis | 39 | 1.57 | 2007 |
| The nuts and bolts of physical synthesis | 2 | 0.38 | 2007 |
| Diffusion-Based Placement Migration With Application on Legalization | 6 | 0.60 | 2007 |
| Hippocrates: First-Do-No-Harm Detailed Placement | 11 | 0.63 | 2007 |
| RQL: global placement via relaxed quadratic spreading and linearization | 28 | 1.35 | 2007 |
| Sensitivity guided net weighting for placement-driven synthesis | 33 | 1.31 | 2005 |
| Diffusion-based placement migration | 30 | 1.36 | 2005 |
| True crosstalk aware incremental placement with noise map | 12 | 0.87 | 2004 |
| Sensitivity guided net weighting for placement driven synthesis. | 0 | 0.34 | 2004 |
