Name
Abstract | ||
|---|---|---|
Monolithic 3D IC overcomes the limitation of the existing through-silicon-via (TSV) based 3D IC by providing denser vertical connections with nano-scale inter-layer vias (ILVs). In this paper, we demonstrate a thorough RTL-to-GDS design flow for monolithic 3D IC, which is based on commercial 2D place-and-route (P&R;) tools and clever ways to extend them to handle 3D IC designs and simulations. We also provide a low-cost built-in-self-test (BIST) method to detect various faults that can occur on ILVs. Lastly, we present a resistive random access memory (ReRAM) compiler that generates memory modules that are to be integrated in monolithic 3D ICs.
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Year | DOI | Venue |
|---|---|---|
2019 | 10.1145/3316781.3323486 | Proceedings of the 56th Annual Design Automation Conference 2019 |
DocType | ISBN | Citations |
Conference | 978-1-4503-6725-7 | 1 |
PageRank | References | Authors |
0.36 | 0 | 11 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Heechun Park | 1 | 13 | 5.44 |
| Kyungwook Chang | 2 | 45 | 8.39 |
| Bon Woong Ku | 3 | 18 | 6.01 |
| Jinwoo Kim | 4 | 1918 | 168.52 |
| Edward Lee | 5 | 4 | 3.79 |
| Dae Hyun Kim | 6 | 505 | 46.95 |
| Arjun Chaudhuri | 7 | 17 | 7.07 |
| Sanmitra Banerjee | 8 | 9 | 4.68 |
| Saibal Mukhopadhyay | 9 | 1288 | 150.52 |
| K Chakrabarty | 10 | 8173 | 636.14 |
| Sung Kyu Lim | 11 | 1688 | 168.71 |