Name
Title | ||
|---|---|---|
3-D NAND Flash Value-Aware SSD: Error-Tolerant SSD Without ECCs for Image Recognition |
Abstract | ||
|---|---|---|
This paper proposes Value-Aware solid-state drive (SSD) with fast access speed and low power consumption by eliminating error-correcting code (ECC). Value-Aware SSD utilizes the error tolerance of image recognition application using a deep neural network (DNN) to enhance reliability. In a previous paper, which proposes Value-Aware SSD, fast ECC decoder is implemented and SSD is evaluated with the 32-bit floating-point data format. On the other hand, in this paper, the proposed Value-Aware SSD is analyzed with 32-bit and 8-bit fixed-point data format and achieves the higher reliability even without ECC by newly proposed two techniques, Critical Bit Error Reduction (CBER) and Middle & Lower Page Error Reduction (M&L-PER). CBER and M&L-PER are proposed for 32-bit and 8-bit data format of application, respectively. These techniques modulate the threshold voltage (
<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$V_{\mathrm {TH}}$ </tex-math></inline-formula>
) distribution of memory cells by recognizing the importance of each stored bit. By proposed CBER, as much as 15% bit error rate (BER) of NAND flash is allowed while the application provides high image recognition accuracy. Even if bit precision is truncated to 8 bit, 3.9% BER is accepted by M&L-PER. The fast read access and low power consumption are realized because ECC is not required. Finally, this paper analyzes the Value-Aware techniques with 3-D multi-level cell (MLC) NAND flash to compare the effects for 3D-MLC and triple-level cell (TLC) NAND flash. |
Year | DOI | Venue |
|---|---|---|
2019 | 10.1109/JSSC.2019.2900866 | IEEE Journal of Solid-State Circuits |
Keywords | Field | DocType |
Image recognition,Error correction codes,Power demand,Integrated circuit reliability,Decoding,Bit error rate | Computer vision,Data format,Error tolerance,Computer science,8-bit,NAND gate,Artificial intelligence,Artificial neural network,Threshold voltage,Power consumption,Bit error rate | Journal |
Volume | Issue | ISSN |
54 | 6 | 0018-9200 |
Citations | PageRank | References |
0 | 0.34 | 0 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Yoshiaki Deguchi | 1 | 3 | 1.52 |
| Toshiki Nakamura | 2 | 7 | 3.41 |
| Atsuna Hayakawa | 3 | 0 | 0.34 |
| K. Takeuchi | 4 | 70 | 29.78 |