Name
Abstract | ||
|---|---|---|
In this paper, we present the world-fastest Internet router architecture that shows 1 + Tbps, which is generally seen as the target throughput of the next-generation Internet routers. We achieve this by introducing an idea of multi-level caches, which is called multi-level Packet Processing Cache (PPC), into Internet routers. We explore an optimal configuration of multi-level PPC in terms of performance, power and area. Our experimental results show that the best achieves 1.02 Tbps (i.e., 3.47x speedup) while reducing power of packet processing by 23.4% at the expense of an area overhead of 20.4%. |
Year | DOI | Venue |
|---|---|---|
2019 | 10.1109/CoolChips.2019.8721336 | 2019 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS) |
Keywords | Field | DocType |
Internet,Throughput,Optimized production technology,Random access memory,IP networks,Power demand,Electric breakdown | Computer science,Computer network,Packet processing | Conference |
ISSN | ISBN | Citations |
2473-4683 | 978-1-7281-1749-2 | 0 |
PageRank | References | Authors |
0.34 | 0 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Kyosuke Tanaka | 1 | 0 | 0.34 |
| Hayato Yamaki | 2 | 0 | 3.04 |
| Shinobu Miwa | 3 | 28 | 13.09 |
| Hiroki Honda | 4 | 84 | 8.72 |