| PredCom: A Predictive Approach to Collecting Approximated Communication Traces | 0 | 0.34 | 2021 |
| Footprint-Based DIMM Hotplug. | 0 | 0.34 | 2020 |
| Evaluating Architecture-Level Optimization In Packet Processing Caches | 0 | 0.34 | 2020 |
| Rpc: An Approach For Reducing Compulsory Misses In Packet Processing Cache | 0 | 0.34 | 2020 |
| Evaluating the Impact of Energy Efficient Networks on HPC Workloads | 0 | 0.34 | 2019 |
| Functionally-Predefined Kernel: a Way to Reduce CNN Computation | 0 | 0.34 | 2019 |
| Multi-Level Packet Processing Caches | 0 | 0.34 | 2019 |
| A Runtime Optimization Selection Framework To Realize Energy Efficient Networks-On-Chip | 0 | 0.34 | 2016 |
| Initial Study Of Reconfigurable Neural Network Accelerators | 0 | 0.34 | 2016 |
| Evaluation of Task Mapping on Multicore Neural Network Accelerators | 0 | 0.34 | 2016 |
| Immediate sleep: Reducing energy impact of peripheral circuits in STT-MRAM caches | 2 | 0.54 | 2015 |
| Profile-based power shifting in interconnection networks with on/off links | 0 | 0.34 | 2015 |
| Runtime multi-optimizations for energy efficient on-chip interconnections1 | 0 | 0.34 | 2015 |
| Evaluation of Core Hopping on POWER7. | 1 | 0.35 | 2014 |
| Data-aware power management for periodic real-time systems with non-volatile memory | 0 | 0.34 | 2014 |
| Performance estimation of high performance computing systems with Energy Efficient Ethernet technology | 2 | 0.38 | 2014 |
| Normally-off computing project: Challenges and opportunities | 1 | 0.35 | 2014 |
| Area-Efficient Microarchitecture For Reinforcement Of Turbo Mode | 0 | 0.34 | 2014 |
| D-MRAM cache: enhancing energy efficiency with 3T-1MTJ DRAM/MRAM hybrid memory | 5 | 0.57 | 2013 |
| Predict-More Router: A Low Latency NoC Router with More Route Predictions | 2 | 0.36 | 2013 |
| Performance modeling for designing NoC-based multiprocessors | 1 | 0.43 | 2013 |
| McRouter: Multicast within a router for high performance network-on-chips | 1 | 0.36 | 2013 |
| Integrating Multi-GPU Execution in an OpenACC Compiler | 7 | 0.69 | 2013 |
| Stepwise sleep depth control for run-time leakage power saving | 0 | 0.34 | 2012 |
| A novel power-gating scheme utilizing data retentiveness on caches | 1 | 0.37 | 2012 |
| Communication Library to Overlap Computation and Communication for OpenCL Application | 1 | 0.37 | 2012 |
| Evaluation Of A New Power-Gating Scheme Utilizing Data Retentiveness On Caches | 0 | 0.34 | 2012 |
| A fine-grained runtime power/performance optimization method for processors with adaptive pipeline depth | 0 | 0.34 | 2011 |
| Evaluation Of Gpu-Based Empirical Mode Decomposition For Off-Line Analysis | 0 | 0.34 | 2011 |
| Parallelizing Hilbert-Huang Transform on a GPU | 0 | 0.34 | 2010 |
| An Effective Replacement Policy Focusing on Lifetime of a Cache Line | 0 | 0.34 | 2010 |
| Dynamic Switching Techniques of Accessing L1/L2 Cache on an SMT Processor | 0 | 0.34 | 2009 |
| Low-Complexity Bypass Network Using Small RAM | 0 | 0.34 | 2008 |
| A Dynamic Control Mechanism for Pipeline Stage Unification by Identifying Program Phases | 3 | 0.52 | 2008 |
| Optimal pipeline depth with pipeline stage unification adoption | 1 | 0.36 | 2007 |
