Paper Info
Title
New Memory Technology, Design and Architecture Co-optimization to Enable Future System Needs
Abstract
While conventional scaling at device level becomes increasingly difficult, the system still requires lower power and lower cost for a given functionality and performance. It is time to bridge the gaps between the technology, device and system teams. Emerging concepts can only make sense by studying their impact on power and performance at system level. This needs to happen early enough in the development to be able to give feedback on the device specifications, hence the need of system simulators. In particular, STT-MRAM has a lot of potential to reduce energy of cache level, and we'll dive deeper into its impact on HPC and mobile applications. DRAM roadmap and even storage needs also seem to accelerate faster than the device roadmap, we'll also open the discussion around these concepts.
Year
DOI
Venue
2019
10.1109/VLSI-TSA.2019.8804641
2019 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)
Field
DocType
ISSN
Dram,Architecture,Computer science,Cache,Design technology,Real-time computing,Embedded system,System level
Conference
1930-8868
ISBN
Citations 
PageRank 
978-1-7281-0943-5
0
0.34
References 
Authors
0
1
Name
Order
Citations
PageRank
Arnaud Furnemont122.76