Enhanced data integrity of In-Ga-Zn-Oxide based Capacitor-less 2T memory for DRAM applications | 0 | 0.34 | 2021 |
New Memory Technology, Design and Architecture Co-optimization to Enable Future System Needs | 0 | 0.34 | 2019 |
Process, Circuit and System Co-optimization of Wafer Level Co-Integrated FinFET with Vertical Nanosheet Selector for STT-MRAM Applications | 0 | 0.34 | 2019 |
Impact of Mechanical Stress on the Electrical Performance of 3D NAND | 0 | 0.34 | 2019 |
A Comparative Analysis on the Impact of Bank Contention in STT-MRAM and SRAM Based LLCs | 0 | 0.34 | 2019 |
Manufacturable 300mm Platform Solution For Field-Free Switching Sot-Mram | 0 | 0.34 | 2019 |
Main memory organization trade-offs with DRAM and STT-MRAM options based on gem5-NVMain simulation frameworks | 1 | 0.34 | 2018 |
A Smaller, Faster, and More Energy-Efficient Complementary STT-MRAM Cell Uses Three Transistors and a Ground Grid: More Is Actually Less. | 1 | 0.39 | 2017 |