Name
Abstract | ||
|---|---|---|
Unlike testing deterministic circuits, where each test pattern is applied only once, testing probabilistic circuits requires multiple pattern repetitions for each test pattern. In this paper, we propose an ATPG algorithm for probabilistic circuits. We use specialized activation and propagation methods to reduce pattern repetitions. Also, we propose to accumulate contribution among different test patterns to further reduce pattern repetitions. Experiments on ISCAS'89 benchmark circuits show the total test length of our proposed method is 24% shorter than a previous greedy method [4]. |
Year | DOI | Venue |
|---|---|---|
2019 | 10.1109/VLSI-DAT.2019.8741869 | 2019 International Symposium on VLSI Design, Automation and Test (VLSI-DAT) |
Keywords | Field | DocType |
Probabilistic Circuits,Test Pattern Compression,ATPG | Automatic test pattern generation,Computer science,Algorithm,Real-time computing,Greedy algorithm,Probabilistic logic,Test compression,Electronic circuit | Conference |
ISSN | ISBN | Citations |
2380-7369 | 978-1-7281-0656-4 | 0 |
PageRank | References | Authors |
0.34 | 5 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Kai-Chieh Yang | 1 | 0 | 0.68 |
| Ming-Ting Lee | 2 | 0 | 0.34 |
| Chen-Hung Wu | 3 | 0 | 1.35 |
| James Chien-Mo Li | 4 | 187 | 27.16 |