Name
Abstract | ||
|---|---|---|
This paper proposes a novel cache coherence protocol - MOESIF - to improve the off chip and on chip bandwidth usage. This is achieved by the reducing the number of write backs to the next level memory and by reducing the numbers of responders to a cache miss when multiple copies of data exists in private caches. Experimental evaluation of various splash-2 benchmark programs on the CACTI 5.3 and CACOSIM simulators reveals that the MOESIF protocol outperforms all other hardware based coherence protocols in terms of energy consumption and access time. MOESIF protocol on an average offers 94.62%, 88.94%, 88.88% and 4.47% energy saving, and 96.37%, 92.83%, 92.77% and 9.21% access time saving over MI, MESI, MESIF and MOESI protocol respectively for different numbers of cores/processors. |
Year | DOI | Venue |
|---|---|---|
2019 | 10.1504/IJES.2019.10022129 | INTERNATIONAL JOURNAL OF EMBEDDED SYSTEMS |
Keywords | DocType | Volume |
cache coherence, MC/MP cache, energy-efficient coherence protocols | Journal | 11 |
Issue | ISSN | Citations |
4 | 1741-1068 | 0 |
PageRank | References | Authors |
0.34 | 0 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Geeta Patil | 1 | 0 | 0.34 |
| Neethu Bal Mallya | 2 | 0 | 0.34 |
| Biju K Raveendran | 3 | 2 | 5.10 |