Name
Abstract | ||
|---|---|---|
This paper presents a 64Gb/s, 2.29pJ/b PAM-4 optical transmitter (TX) utilizing a VCSEL. To improve the power efficiency, the TX adopts a quarter-rate architecture consisting of a quadrature clock generator and a 4:1 MUX. By employing an asymmetric push-pull FFE, high-speed PAM-4 signaling based on a VCSEL can be achieved. It is fabricated in a 65nm CMOS technology, occupying an active area of 0.278mm(2). |
Year | DOI | Venue |
|---|---|---|
2019 | 10.23919/VLSIC.2019.8777952 | 2019 SYMPOSIUM ON VLSI CIRCUITS |
Keywords | Field | DocType |
VCSEL, PAM-4 transmitter (TX), CMOS | Electrical efficiency,Transmitter,Clock generator,Computer science,Multiplexer,Electronic engineering,CMOS,Quadrature (mathematics),Vertical-cavity surface-emitting laser,Very-large-scale integration | Conference |
Citations | PageRank | References |
0 | 0.34 | 0 |
Authors | ||
8 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Jeongho Hwang | 1 | 2 | 2.14 |
| Hong Seok Choi | 2 | 0 | 0.68 |
| Hyungrok Do | 3 | 0 | 3.04 |
| Gyu-Seob Jeong | 4 | 21 | 9.00 |
| Daehyun Koh | 5 | 0 | 1.69 |
| Kwanseo Park | 6 | 22 | 9.60 |
| sungwoo kim | 7 | 37 | 5.93 |
| Deog-Kyoon Jeong | 8 | 626 | 119.05 |