Paper Info
Title
A 1.4GHz 20.5Gbps GZIP decompression accelerator in 14nm CMOS featuring dual-path out-of-order speculative Huffman decoder and multi-write enabled register file array
Abstract
A 33,464μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> GZIP decompression accelerator is fabricated in 14nm CMOS, achieving industry-leading 20.5Gbps throughput. The design features out-of-order speculative Huffman decoder to break the fundamental serial dependency resulting in 69% higher decode throughput. The hybrid dual-path decoder provides 2.3× higher performance with multi-write enabled register-file array increasing decompression throughput by up to 41%. The arithmetic-architecture-circuit co-optimized design operates at 1.4GHz at 750mV, 25°C with peak measured energy-efficiency of 1.86pJ/code at 280mV, 2.7× higher than previously reported implementations.
Year
DOI
Venue
2019
10.23919/VLSIC.2019.8777934
2019 Symposium on VLSI Circuits
Keywords
Field
DocType
hybrid dual-path decoder,decode throughput,multiwrite enabled register file array,dual-path out-of-order speculative Huffman decoder,GZIP decompression accelerator,arithmetic-architecture-circuit co-optimized design,decompression throughput,fundamental serial dependency,14nm CMOS,frequency 1.4 GHz,voltage 750.0 mV,voltage 280.0 mV,temperature 25.0 degC,size 14.0 nm
Decompression,Computer science,Parallel computing,Register file,Radio frequency,CMOS,Huffman coding,Decoding methods,Throughput,Out-of-order execution
Conference
ISSN
ISBN
Citations 
2158-5601
978-1-7281-0914-5
0
PageRank 
References 
Authors
0.34
0
12
Name
Order
Citations
PageRank
Sudhir Satpathy100.68
Vikram Suresh2193.00
Raghavan Kumar37312.56
Vinodh Gopal4384.28
James Guilford500.68
Mark Anders631550.81
Himanshu Kaul745651.07
Amit Agarwal869372.95
S. K. Hsu952152.06
Ram Krishnamurthy1065074.63
Vivek De113024577.83
S. Mathew1246276.59