Name
Title | ||
|---|---|---|
A 2048-Neuron Spiking Neural Network Accelerator With Neuro-Inspired Pruning And Asynchronous Network On Chip In 40nm CMOS |
Abstract | ||
|---|---|---|
A 40nm, 2.56mm
<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>
, 2048-neuron globally asynchronous locally synchronous (GALS) spiking neural network (SNN) chip is presented. For scalability, we allow neurons to specialize to excitatory or inhibitory, and apply distance-based pruning to cut communication and memory. An asynchronous router limits the latency to 1.32ns per hop. The reduced traffic and lower latency allow the input channel to be parallelized to achieve 7.85GSOP/s at 0.7V, consuming 5.9pJ/SOP. |
Year | DOI | Venue |
|---|---|---|
2019 | 10.1109/CICC.2019.8780116 | 2019 IEEE Custom Integrated Circuits Conference (CICC) |
Keywords | Field | DocType |
spiking neural network,asynchronous networkon-chip,distance-based pruning,deadlock handling | Asynchronous communication,Computer architecture,Synchronization,Globally asynchronous locally synchronous,Latency (engineering),Computer science,Electronic engineering,Chip,Router,Spiking neural network,Scalability | Conference |
ISSN | ISBN | Citations |
0886-5930 | 978-1-5386-9396-4 | 1 |
PageRank | References | Authors |
0.35 | 3 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Sung-Gun Cho | 1 | 2 | 2.06 |
| Edith Beigne | 2 | 536 | 52.54 |
| Zhengya Zhang | 3 | 502 | 48.41 |