Name
Abstract | ||
|---|---|---|
This paper presents a 2× half-baud-rate clock and data recovery technique that locks to the edge by performing 2× oversampling at half-baud-rate (every other UI). A test-chip was fabricated in TSMC 28nm HPC CMOS technology demonstrating a 30 Gb/s 2× half-baud-rate CDR with a Tyco 5” channel with 13.06 dB loss at Nyquist. The total power consumption is measured to be 79.2 mW (FOM of 2.64 pJ/bit) for 30 Gb/s PRBS31 input data. |
Year | DOI | Venue |
|---|---|---|
2019 | 10.1109/CICC.2019.8780251 | 2019 IEEE Custom Integrated Circuits Conference (CICC) |
Keywords | Field | DocType |
CMOS,Receiver,CDR,Clock and Data Recovery | Oversampling,Computer science,Communication channel,CMOS,Electronic engineering,Data recovery,Jitter,Nyquist–Shannon sampling theorem,Baud,Detector | Conference |
ISSN | ISBN | Citations |
0886-5930 | 978-1-5386-9396-4 | 0 |
PageRank | References | Authors |
0.34 | 3 | 6 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Danny Yoo | 1 | 62 | 7.08 |
| Mohammad Bagherbeik | 2 | 1 | 0.72 |
| Wahid Rahman | 3 | 6 | 1.61 |
| Ali Sheikholeslami | 4 | 416 | 54.27 |
| Hirotaka Tamura | 5 | 204 | 32.19 |
| Takayuki Shibasaki | 6 | 66 | 12.00 |