Paper Info
Title
Built-in Self-Test for Inter-Layer Vias in Monolithic 3D ICs
Abstract
Monolithic 3D integration provides massive vertical integration through the use of nanoscale inter-layer vias (ILVs). However, high integration density and aggressive scaling of the inter-layer dielectric make ILVs especially prone to defects. We present a low-cost built-in self-test (BIST) method to detect opens, stuck-at faults (SAFs), and bridging faults (shorts) in ILVs. Two test patterns-all-1s and all-0s-are applied to the input side of a set of ILVs (e.g., making up a bus between two tiers). On the adjacent tier (the output side of the ILVs), the test responses are compacted to a 2-bit signature through space compaction. We prove that this compaction solution does not introduce any fault aliasing. Simulations results using HSPICE and M3D benchmark designs show that the proposed BIST method requires low area overhead and test time, but provides effective fault localization and the detectability of a wide range of resistive faults.
Year
DOI
Venue
2019
10.1109/ETS.2019.8791515
2019 IEEE European Test Symposium (ETS)
Keywords
Field
DocType
monolithic 3D integration,massive vertical integration,nanoscale inter-layer vias,ILVs,high integration density,aggressive scaling,inter-layer dielectric,adjacent tier,test responses,space compaction,fault aliasing,M3D benchmark designs,BIST method,effective fault localization,resistive faults,low area overhead,HSPICE,open fault detection,stuck-at fault detection,built-in self-test method,monolithic 3D ICs,bridging fault detection,time 1.0 s,word length 2 bit
Resistive touchscreen,Computer science,Bridging (networking),Electronic engineering,Aliasing,Vertical integration,Scaling,Built-in self-test
Conference
ISSN
ISBN
Citations 
1530-1877
978-1-7281-1174-2
1
PageRank 
References 
Authors
0.36
7
6
Name
Order
Citations
PageRank
Arjun Chaudhuri1177.07
Sanmitra Banerjee294.68
Heechun Park3135.44
Bon Woong Ku4186.01
K Chakrabarty58173636.14
Sung Kyu Lim61688168.71