Paper Info
Title
Design of a 55-nm SiGe BiCMOS 5-bit Time-Interleaved Flash ADC for 64-Gbd 16-QAM Fiberoptics Applications
Abstract
We present the architectural, circuit topology, transistor-level schematics, and layout design considerations for the highest sampling-rate single-chip ADC reported to date in any semiconductor technology. The circuit uses a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$2\times $ </tex-math></inline-formula> time-interleaved architecture integrating two track-and-hold amplifiers, each driving a 5-bit flash sub-ADC sampled at 64 GHz in antiphase. For testing purposes, the chip also incorporates a time-interleaved 128-GS/s thermometer-coded 5-bit current steering DAC. The performance of the ADC-DAC combo, including the SFDR and the effective number of bits of 4 bits up to 32-GHz input signals, was characterized on die and includes the impact of the DAC. The power consumption and layout footprint of the ADC, critical for operation at 128 GS/s, were minimized by employing novel 1-mA Cherry-Hooper comparators and quasi-current-mode logic MOS-HBT latches with active peaking, which reduced the footprint of each of the 64 ADC-lanes to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$10\,\,\mu \text{m}\,\,\times $ </tex-math></inline-formula> 70 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> . The total power consumption of the ADC is 1.25 W and the total die area of the ADC-DAC chip is 1.1 mm <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times $ </tex-math></inline-formula> 1.9 mm.
Year
DOI
Venue
2019
10.1109/JSSC.2019.2917155
IEEE Journal of Solid-State Circuits
Keywords
Field
DocType
Silicon germanium,Clocks,BiCMOS integrated circuits,Power demand,FinFETs,Layout,Latches
BiCMOS,Comparator,Computer science,Spurious-free dynamic range,Effective number of bits,Electronic engineering,Chip,Flash ADC,Amplifier,Topology (electrical circuits)
Journal
Volume
Issue
ISSN
54
9
0018-9200
Citations 
PageRank 
References 
3
0.51
0
Authors
3
Name
Order
Citations
PageRank
Alireza Zandieh130.51
Peter Schvan214737.29
Sorin P. Voinigescu322153.57