Paper Info
Title
3DTUBE: A Design Framework for High-Variation Carbon Nanotube-based Transistor Technology
Abstract
Various emerging technologies have shown great potential of supplementing silicon transistors as Moore's law slows down. One such disruptive technology, carbon nanotube field-effect transistors (CNFETs), is one of the most promising competing technologies available, offering exceptional electrostatic properties. Furthermore, their low-temperature manufacturing process and low power consumption make these devices perfect candidates for 3D integration. However, due to the infancy of their manufacturing process, high defect densities, and variation issues, chip designers are not encouraged to consider these emerging technologies as a stand-alone replacement for Si-based transistors. Hence, to commercialize these new technologies, new architectural and circuit modifications that can work around high-fault rates are required, improving performance comparable to Silicon, while the manufacturing process is perfected.This paper proposes a design flow framework that can be used for large-scale chip production while mitigating yield and variation failures to bring up CNT-based technology, using a reliable reconfigurable architecture. The proposed framework can efficiently support high-variation technologies by providing protection against manufacturing defects at multiple granulari-ties: module and pipeline-stage levels.To incorporate different CNT-based transistor manufacturing processes, this work builds a flexible variation model and a CMOS-based CNT design library that can be used to synthesize physical CNFET-based processor designs over a range of 0.4 to 0.7 V. Based on the variation observed in the synthesized design, a reliable CNT-based 3D multi-granular reconfigurable architecture, 3DTUBE, is presented to overcome the manufacturing difficulties in the technology. For 0.4 V to 0.7 V, 3DTUBE provides up to 6.0× higher throughput and up to 3.1× lower Energy-Delay Product compared to a silicon-based multi-core design evaluated at 1 ppb transistor failure rate, which is 10,000× lower in comparison to CNFETs failure rate.
Year
DOI
Venue
2019
10.1109/ISLPED.2019.8824874
2019 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED)
Keywords
Field
DocType
reliability,high-variation,reconfiguration,3D framework,CNFET
Computer science,Failure rate,Electronic engineering,Design flow,Chip,CMOS,Emerging technologies,Throughput,Transistor,Control reconfiguration
Conference
ISBN
Citations 
PageRank 
978-1-7281-2955-6
0
0.34
References 
Authors
8
4
Name
Order
Citations
PageRank
Aporva Amarnath1395.18
Javad Bagherzadeh211.41
Jielun Tan332.41
Ronald G. Dreslinski4125881.02