Name
Abstract | ||
|---|---|---|
Researchers have been trying to exploit the temperature effect inversion (TEI) phenomenon to improve energy efficiency of system-on-chip (SoC) designs without sacrificing its performance. However, TEI-aware low power methods have a critical limitation in that they can only be applied to components within the SoC that do not contain long (global) wires. This is because wire delays continue to increase with rising temperatures irrespective of the operating supply voltage level, which tends to cancel out positive effects of the TEI phenomenon in SoCs. To tackle this limitation and thoroughly utilize the TEI-aware methods, this paper presents new TEI-inspired SoC platform (called TIP), which relies on network-on-chip architecture (called μNoC) to realize system interconnects. The μNoC successfully reduces the total number and length of global wires. By fabricating a TIP prototyping chip in Samsung 28nm FD-SOI technology, we verify the effectiveness of TIP. Extensive post-fabrication measurements demonstrate that the chip while continuing to operate at a target 50MHz clock frequency can lower its supply voltage from 0.54V to 0.48V at 25°C and to 0.44V at 80°C, which results in up to 35% power saving. |
Year | DOI | Venue |
|---|---|---|
2019 | 10.1109/ISLPED.2019.8824925 | 2019 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED) |
Keywords | Field | DocType |
Ultra-low power,system-on-chip,network-on-chip,temperature effect inversion | System on a chip,Efficient energy use,Inversion (meteorology),Computer science,Voltage,Electric power system,Network on a chip,Electronic engineering,Chip,Clock rate | Conference |
ISBN | Citations | PageRank |
978-1-7281-2955-6 | 0 | 0.34 |
References | Authors | |
9 | 5 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Kyuseung Han | 1 | 58 | 7.86 |
| Sukho Lee | 2 | 0 | 1.35 |
| Jae-Jin Lee | 3 | 27 | 8.69 |
| Woojoo Lee | 4 | 104 | 10.96 |
| Massoud Pedram | 5 | 7801 | 1211.32 |